Automatic Generation of Polynomial-Basis Multipliers in GF (2) using Recursive VHDL

Multiplication in GF (2) is very commonly used in the fields of cryptography and error correcting codes. Automating the design process for these multipliers could reduce the cost and development time of hardware implementations. In this project, we present a general design for these multipliers and a strategy to generate them automatically given the precision of the operands and the irreducible polynomial which defines the field. In particular, the generation and use of tree structures based on a previously proposed recursive VHDL technique is compared with other Galios Field multipliers. It is shown that the final result of this automatic design tool is very competitive with some specialized designs presented in the literature, with the advantage that it can be adjusted to any type of trinomial or pentanomial in the IEEE standard.